It is well known that semiconductor devices include an interconnect stricture having alternating layers of conductive interconnects and dielectric material. The conductive interconnects are employed to connect the active and passive devices formed in a semiconductor chip. After the semiconductor devices have been formed in or on a central or inner portion of the semiconductor chip, a seal ring or other anchor structure is typically formed in an outer region of one or more of the dielectric layers of the interconnect structure in an outer edge region of the chip around the active devices. Generally, the seal ring protects the semiconductor devices from contaminants and prevents the stacked layers of conductive interconnects and insulating dielectric layers from cracking or delaminating, such as by providing stress relief. The matrix of conductive interconnects and dielectric layers are especially susceptible to cracking and delaminating during the die sawing or other processes employed to separate the multiple chips formed on a wafer into individual chips or dies, and during the molding process employed to encapsulate individual dies in packaging material.
In a typical semiconductor device fabrication process, a large single crystal of silicon is sliced into wafers which are typically 6 inches to 12 inches in diameter. Using deposition and photolithographic techniques, alternating layers of conductive material and dielectric material are applied to the surface of the wafer to form logic devices and the interconnect structure, including the seal ring in an outer portion of the chip surrounding the logic devices formed in an inner portion of the chip. Generally, these layers are deposited at high temperatures and have very different thermal coefficients. Consequently, substantial stress is generated when the wafer undergoes the thermal cycling inherent to the processes employed to form the interconnect structure. After depositing a final passivation layer to protect the logic devices, the wafer is sawed or otherwise separated into individual dies. The dies are installed into a package. The package is typically made of either ceramic (for high power/high cost devices) or plastic (for low power/low cost devices).
As mentioned above, these fabrication processes create intrinsic stresses in the dielectric layers (e.g., silicon dioxide insulating layers employed to electrically isolate the conductive interconnects), the conductive interconnects, and the passivation layer. When the die is encapsulated, additional stresses are generated by the expansion differential between the die and the molding compound as the die cools to room temperature. Moreover, the adhesive bond between the molding compound and adjacent layers may delaminate, causing forces and stresses to concentrate on the surface of the die. If the stresses are high enough, it is possible for the passivation layer and/or the dielectric layers to crack. Once this has occurred, moisture can penetrate into the conductive interconnects which can cause corrosion and electrical shorting and lead to device failure.
Moreover, conventional seal rings include stacks of vertically aligned conductive vias substantially spanning the height of the seal ring. That is, each via extends between an upper surface of one of the conductive interconnects and a lower surface of another, overlying conductive interconnect. As such, the vias provide insufficient structural integrity, and do not provide adequate stress relief to compensate for the stress accumulation inherent to existing fabrication processes.
Accordingly, what is needed in the art is a seal ring that overcomes the problems discussed above.